The present invention relates generally to digital computers and more specifically to memory checking circuitry.
Most present day medium and large scale computers have the capability for the addition or deletion of memory capacity through the addition or deletion of memory modules. These memory modules quite often are operated asynchronously from one another and from other modules (e.g., Central Processing Units, Input/Output Controllers, etc.) within the computer. Furthermore these memory modules usually have their own addressing circuitry (i.e., holding registers, translators, etc.) to permit ease of interface to other modules within the computer. It is desirable to verify the correct operation of this addressing circuitry. The most common method is to write unique data into each (or each worst case) addressable location of the memory and read the unique data for comparison with what was written. This technique has the advantage of being executed under software control obviating the need of special test equipment. This technique is somewhat disadvantageous, however, because the writing and reading of many addressable locations is time consuming and necessitates relatively large temporary storage capacity to prevent data from being destroyed. Furthermore, the use of addressable locations to test the addressing circuitry may cause errors or ambiguities in the test results if the memory arrays malfunction.
The present invention perserves the desirability of software controlled testing of the addressing circuitry while eliminating the undesirable aspects of utilizing the memory arrays during testing of the addressing circuitry.